In the field of computers, binary memory is common. In binary memory, of course, each "bit" is either a 1 or a 0 and, therefore, to represent data that can have 2.sup.n states, "n" bits are required. Thus, one bit can have two states (i.e. 2.sup.1), two bits can be used to represent four states (i.e. 2.sup.2), and so forth. Analog memory would provide the ability to represent many more states in a smaller space. For example, if each "bit" could have four setable and detectable states, four bits of memory could represent 256 states (i.e. 4.sup.4) instead of the sixteen states that four binary bits can assume (i.e. 2.sup.4) .
The need for analog memory is known in the art and attempts have no doubt been made by those skilled in the art to arrive at a viable analog memory structure. To the best of the knowledge of the inventors herein, no successful analog memory has been reported. Moreover, since the primary usefulness for analog memory is in instances where space, weight, etc. are principal considerations (such as space applications), a successful analog memory must also be able to function in the hostile environments such applications provide. The need for analog memory is also exhibited in special purpose computing applications, such as artificial neural networks.
In reviewing the background art available in the field, the inventor herein noted several prior U.S. patents which disclosed memory structures which, in some case, could be misinterpreted as being the same as the analog memory structure of the present inventors to be described hereinafter. In the interest of putting such misinterpretations to rest at an early stage of this disclosure so that the novelty of the present invention will be readily apparent, a brief commentary on several of these patents follows hereinafter.
Lutes (U.S. Pat. No. 4,455,626)--While the Lutes memory appears to propose a structure similar to that of the present invention, those skilled in the art will recognize that the Lutes memory is (and can only be) a binary memory. As will be described in detail with respect to the disclosure of the present invention hereinafter, the choice of materials and structure of the Lutes memory is such as to require more layers and a more complex implementation process. Most important, however, the materials employed simply could not function as a viable analog memory.
Dimyan (U.S. Pat. No. 4,360,899)--This is definitely a binary memory and could not be an analog memory.
Bergman (U.S. Pat. No. 3,577,134)--Bergman discusses a multilayer memory; but, with emphasis on binary storage with DRO/NDRO operation. There is no discussion of analog memory capabilities.
Lampe (U.S. Pat. No. 4,722,073)--Like Dimyan, this is definitely a binary memory and could not be an analog memory.
Coleman (U.S. Pat. No. 4,831,427)--This memory uses a transistor structure where the gate is ferromagnetic in place of standard conductors. As will be seen from the discussion of the present invention which follows, this is completely different from the structure of this invention where transistors which are standard CMOS implementations in tandem are used with an analog memory cell.
Daughton (U.S. Pat. No. 4,731,757)--This disclosure is definitely a binary memory and the geometry and materials employed are not suitable for implementing analog memory. Also, there is no explicit use of embedded transistors as in the memory elements of the present invention.
Daughton (U.S. Pat. No. 4,780,848)--This later Daughton disclosure makes no use of transistors in tandem as in the memory elements of the present invention. Moreover, the memory geometry and the materials employed do not appear to be useful for implementing analog memory.